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CS154 Computer Design Lab
Lab5a Adding instruction cache
Please read ALL instructions carefully. Only properly submitted assignments will be graded. Make sure to create a zipfile, named by your student id, and submit required files in it.
Specification
This lab implements a small, 1-cycle instruction cache. It is a 2-way set-associative cache (see block diagram here) with a block size of 4 bytes and a total of 8 blocks. Your new cache module will sit between the PC and the memory in your Lab 5 design. Reuse as much of the Lab 5 datapath as you can. Submit a full block diagram of the full data path as the specification.
Design
1. Copy and modify the mem.vhd behavioral design to make it into the cache (cache.vhd). You need to add ports, such as “Miss” (out) and “Reset_N” (in). Set valid bits to ‘0’ on reset.
2. A set-associative cache needs a replacement policy. Design the LRU replacement using one lru bit per set. The value of the lru bit indicates which of the two lines in the set is to be replaced. Initialize the lru bits to ‘0’ on reset. Replace the cache line pointed by the lru bit for the set on a miss.
3. Add cache.vhd to the complete datapath. You will also add a “Dready” output to the memory design, it will be used to signal when the memory data is ready on reads (and memory ready for next op on writes). The memory latency is a design parameter, let’s make it 3.5 clock cycles.
4. Add cache_latency and memory_latency constants to Glob_dcls. Modify the memory module (mem.vhd ) to have a 4-cycle latency.
Verification
You need to test your Icache as part of the full datapath that you have not yet tested. Note that this does not require verifying an actual instruction execution, just the Ifetch step. as listed below.
- Verify your Icache design (including internal reset of valid bits)
- Test instruction fetch in the full datapath for a hit and a miss
Generate the control signals at the right time in your testbench for each test case. Use a clock cycle of 40 ns. You can set internals signals at any time in Modelsim simulation for testing purposes (use Edit-> Force to set a signal to a specific value and for how long. Set `Kind` to Freeze).
Submission:
Please submit the specification :
A block diagram of the Icache
A block diagram of the updated full datapath
Please submit your design and verification:
HDL design of the Icache and the test bench
Screenshots of Waveform
Both the implementation and test code will be graded. You will also be graded on coding style and code comments.