There are two sections to this resit assessment. Section I requires implementation of HDL programs and Section II requires the implementation of assembly language.

SECTION I

Your task is to design and implement a circuit in hdl which takes two 2-bit numbers (A, B) and (C, D) as input and produces a 3-bit output (E, F, G).

The final circuit has 6 inputs in total (f1, f0, A, B, C, D) and 3 outputs (E, F, G).

The function of the circuit is determined by the two inputs f1 and f0.

The truth tables below define the operation of the circuit for each combination of f1 and f0.

You must only use the built-in AND, NAND, OR, NOR, NOT, Mux, XOR or DMux chips.

The test files provided (.tst and .cmp) can be used to test each output of a chip. For example FZero1.tst tests the F output of the chip FZero.hdl and FZero2.tst tests the G output of FZero.hdl. [9 marks]

(b) Combine all four circuits into one circuit which takes all six inputs and three outputs and test it to ensure it produces the correct output depending on the value of the inputs f1 and f0. Call the chip FALL. You can test this chip using FALL.tst but may wish to create further tests before submission. The value of output is undefined (can be either 0 or 1) unless (f1, f0) = (0, 0) You must only use the built-in AND, NAND, OR, NOR, NOT, Mux, XOR or DMux chips.

(c) Stretch Activity

When performing computational operations it is often useful to be able to execute a sequence of operations, each one using the output of the previous step as an input to the next step. For example to OR 3 values X OR Y OR Z you might first calculate X OR Y and then on the next step apply OR Z to the previous output (X OR Y ).

For this task adapt the circuit FALL so that it can combine a sequence of operations defined by different values for f1 and f0 at each step, by enabling the outputs Ft and Gt of step t to be used (feedback) as the inputs for the next operation Ct+1 and Dt+1 for step t + 1. You should also add a further input (Load) to the chip which when Load = 1 will enable you to load new inputs to Ct and Dt and when set to 0 sets Ct+1 = Ft and Dt+1 = Gt . The Load input will allow you to manually set the values of C and D at the start and during the sequence if required.

Call this chip FSEQ. You can test this chip using FSEQ.tst but may wish to create further tests before submission.

You must only use the built-in AND, NAND, OR, NOR, NOT, Mux, DMux, XOR or DFF chips. [7 marks]

SECTION II

In a Feistel cipher the plaintext, P, to be encrypted is split into two equal size parts L0 and R0 such that P = L0R0. A function F is applied to one half of the plaintext, combined with a key, and the result is XOR’d with the other half of the plaintext.

(b) Write a program (Rotate.asm) in HACK assembly that implements an algorithm to rotate the bits of a 16-bit number left (Least Significant bit (LSb) to Most

Significant bit (MSb)). The original number should be stored in RAM[3] the number of times to rotate the bits should be in RAM[4] and the result stored in RAM[5], i.e. 1010111100000000 rotated left 3 times would be 0111100000000101 where the MSb is used to replace the LSb. [12 marks]

(c) Write a program (FeistelEncryption.asm) in HACK assembly, that implements the described Feistel encryption system. The initial key, K0, will be stored in RAM[1], and the 16-bit plaintext will be stored in RAM[2]. The result of the encryption should be stored in RAM[0]. [12 marks]

[Total for Section II 30 marks]

Tools required to simulate the hardware and CPU are provided on Minerva under Learning resources: Software.

Please ensure the files you upload work with the test files provided and use the filenames provided in this sheet. Do not alter the format of the lines of these test files in any way. The spacing in each line needs to be preserved You are of course welcome to build your own test files in the same format or add to these files.

Ensure the files you upload pass the submission tests provided on Gradescope. These are not necessarily the same tests as those that will be used to grade your submission.

4. Assessment criteria and marking process

This coursework will be marked using Gradescope. Feedback will be provided through Gradescope and example solutions discussed in class.

Marks are awarded for passing the automated tests on the submitted programs detailed below.

Submitted code should provide suitable comments where possible.

Links to submit your work can be found on Minerva under Assessment and feed back/Submit my work.

For section I submit only your hdl files, uploaded individually. Ensure you use only the filenames provided in this specification sheet. The names must match the specification exactly, including the use of upper and lower case characters i.e. FZero.hdl is valid however, fzero.hdl or FZero.HDL are not valid.

For section II submit only your asm files.

7. Academic misconduct and plagiarism

Academic integrity means engaging in good academic practice. This involves essential academic skills, such as keeping track of where you find ideas and information and referencing these accurately in your work.

By submitting this assignment you are confirming that the work is a true expression of your own work and ideas and that you have given credit to others where their work has contributed to yours.

There is a three-tier traffic light categorisation for using Gen AI in assessments.

• This assessment is red category. AI tools cannot be used.

No marks will be awarded for tests which fail or use of chips other than those listed.