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ELEC 2200

Digital Logic Circuits

Summer 2025

In-Class Exercise for Module 2 – No. 2

Monday, July 7, 2025

Assume a positive edge-triggered D flip-flop (“X”) and a D latch (“Y”) are supplied the signals given on the timing chart, below. Plot the response of each, noting the initial states. Assume the propagation delays of the flip-flop and latch are negligible relative to the period of “C”.