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CS154 Computer Design Lab

Lab5 Complete Datapath Design

Please read ALL instructions carefully. Only properly submitted assignments will be graded. Make sure to create a zipfile, named by your student id, and submit required files in it.

Specification

This lab implements the full datapath. Complete the design of the data path by adding all the logic necessary to support LD, ST, BNE, BEQ, and JMP instructions, as well as support for executing the I-format ALU instructions. The instructions in the following table should be supported by your design. Reuse as much of the Lab 4 datapath as you can, adding a memory, IR, PC, MDR, multiplexers, sign extenders, etc. Submit a full block diagram of the datapath as the specification.

To clarify JMP and BEQ/BNE semantics: in all of these the offset is a word offset in the IR.  The Memory Component takes a byte address.  So offsets need to be converted to bytes.

1.     Jump: offset is 26 bits.  Shift left by 2b to get a 28bit value Off.  Concatenate with 4 high-order bits of the PC: PC<= PC(31 downto 28) & Off;

2.     BNE/BEQ: offset is 16 bits.  Shift left by 2b to get an 18bit value.  Sign exted it and add to the PC.

Also, note that the full processor diagram in Lec. 9 contains a unit called ALU control - which is external to the datapath.  It has a 2b input from the main control unit called ALUOp and the funct field from the IR as the 2^nd  input. Its output is the 3b opcode for the ALU.  Per CS152, here is how the ALU control generates opcodes:

   ALUOp = 00 - opcode is Add

   ALUOp = 01 - opcode is Subtract

   ALUOp = 10 - opcode is determined by the funct field in the instruction

The "func_out" field is an output port on the datapath because the ALU control is outside the datapath.  This is also why the 3-bit control signal "ALUControl", which selects an ALU operation, needs to be an input port.    Finally, note that per CS152 book, this ALU control unit does not handle operations for I-type ALU instructions.

Design

Design the complete datapath and a testbench to test the functionality of the datapath entity.

The template VHDL files for the module (lab5.vhd), global declaration package (Glob_dcls.vhd) and memory module ( mem.vhd ) have been provided to you. The interface (that is, ports) is already defined. You need to design the architecture for both. Do not make any change to the interface.

Please see the updated glob_dcls.vhd here. Line 21 has been modified. The range should be "0 to 31" instead of "31 downto 0".

Verification

You need to test parts of the full datapath that you have not yet tested.  Note that this does not require verifying an actual instruction execution, just any steps of one, as listed below.

1. Instruction fetch and PC update
2. Load address computation + the actual load from memory
3. Store address computation + actual store to memory
4. PC update on branch taken

Generate the control signals at the right time in your testbench for each test case. Use a clock cycle of 40 ns.  You can set internals signals at any time in Modelsim simulation for testing purposes (use Edit-> Force to set a signal to a specific value and for how long.  Set `Kind` to Freeze).

Submission:

Please submit the specification :   

A block diagram of the complete datapath

Please submit your design and verification: 

HDL design and test bench

Screenshots of Waveform

Both the implementation and test code will be graded. You will also be graded on coding style and code comments.