CSE12 Lab 1: Intro to Logic Simulation

Final Submission must be made by the due date at 11:59 PM using Gradescope.

(You can submit many times.  Your grade will be the grade of your last submission, prior to the deadline).

Minimum Submission Requirements

●    You will be submitting the following files:

○ part_a.dig

○ part_a.txt

○ part_b.dig

○ part_b.txt

○ part_c.dig

○ part_c.txt

Note

To  make  life  easier  on  yourself,  create  a  directory  called:

CSE12_Labs, under that directory create subdirectories: Lab1, Lab2, Lab3,Lab4.  This will keep you organized for the rest of the quarter.  You will not be submitting the directories with the lab.  This suggestion isjust to keep your work organized.

Objective

This lab will introduce you to a schematic entry and logic simulation program called Digital. In this lab you will practice creating truth tables and implementing logic based on those truth tables.

To install Digital:

1. Ensure you have a Java Runtime Environment (or JRE) on your computer. You can download it included in the JDK (Java Development Kit) which would also allow you to write your own Java programs. You can download the JDK from here. This location has installation options for Mac, Windows and Linux. You will most likely want the 64-bit version.

2. Download Digital.zip and uncompress it.

3. In the Digital folder open Digital.jar to run it.

Tutorial

Before starting the lab assignment, follow this tutorial on how to build a very simple circuit.

●    Start a new circuit by inserting an input, graphically depicted as form: into the graph from Components->IO.

●    Place a second input below the first. You can either select “input” again from Components->IO or you can click on the input icon in the upper right toolbar, which displays recently used components.

●    Select an “Exclusive Or” (XOR) depicted as:         from Components- >Logic and place it to the right of the two inputs. NOTE: If XOR gate has not yet been discussed in class as of you reading this sentence, proceed to the section Appendix.

●    Select an output ◎ from Components->IO and place it to the right of the XOR gate.

●    Connect the inputs to the XOR gate by clicking on the red dot of the input and then on one of the XOR’s blue dots.

●    Connect your XOR gate to your output in the same way.

●    Now that you have a functioning circuit, you can start a simulation by clicking the Play button in the toolbar. Test some different inputs to ensure the XOR gate works the way you want it to.

●    Once you have explored the functioning circuit, stop the simulation with the

Stop button 回 in the toolbar.

●    Finally,  label  your inputs and output by  right  clicking on them (control-click on Mac.)

Resources

You can find the English documentation for Digital under

Help-> Documentation:

You can also find the documentation in various other languages here

Finally, a video walk-through of the tutorial can be found here

Specification

For all parts of the design, assume an ON LED represents “1” and an OFF LED represents “0. ”

Part

A

For Part A, implement the truth table below using either CANONICAL Sum of Products (SOP) or Product of Sums (POS) using gates, not transistors.

Label your inputs and outputs exactly as is shown below (wrong case or

spaces will fail the auto-grade), as they will be referenced in grading.

You MUST not simplify the SOP/POS expression at this stage!

To quickly check if your circuit is correct, you can generate a truth table

for your current circuit by selecting Analysis->Analysis:

This will bring up the truth table that your circuit currently represents.

For this assignment, you will be submitting the plain text output of a

simplified boolean function that is representative of your truth table as

well as the digital file. Once you have correctly implemented a particular

circuit, you can save the output of this boolean equation through an

automated analysis by selecting:

Analyses -> Analyses -> File -> Export Plain Text.

Copy paste the text from the pop up window into a text file. Save it as

part_a.txt/ part_b.txt/ part_c.txt depending on the requirement. Make sure

the encoding of the text file is UTF-8 or plain ASCII. If you are on Windows, we recommend to use Notepad++ as a simple text editor. After installing it,

simply go to Notepad++ -> Encoding and check that it is UTF-8. In general, you should use plain text editors like Notepad++ for coding assignments in High

Level Languages. Word Processors will not work for that purpose. Note that

sometimes you will get more than one simplified boolean equation.  Please

submit all of them exactly as given to you by the Analyses tool as explained above.

Finally, you must create an automated test to verify your results. You can create

a test component by selecting Components->Misc:

Once placed, you can right click on the test to name it, and hit “edit” to

enter the expected output of your circuit. The first line should contain

your input names and your output name, separated by a space, while the

following lines should contain your expected truth table values:

Note: The truth table in the diagram above does not match the intended

truth table in Part A, and is only meant to serve as an example. The truth

table you get should match the one you are targeting. Make sure you use the

exact same capitalization and order for the signal names.

Name your test “part a test”. You can automatically run your test by selecting Simulation->Run Tests:

Once you have confirmed that your test runs correctly, save the plain text export of your automated analysis as part_a.txt, and the digital file as part_a.dig. For all your .dig files, you make sure that for your text file you are following UTF-8 encoding as well. Usually, Windows users don’t need to worry about this but other systems do tend to use different encodings.

Part

B

For Part B, implement a simplification of the following expression using the

rules explained in class (using gates, not transistors):

out0＝(w0)(q)(2)＋(0)(in1)(2)＋(in0)(q)(n2)＋(in0)(in1)(2)＋(in0)(in1)(in2)

Once you have simplified the expression to its most basic form, create the circuit in Digital. Once you have created the circuit, create a test named “part b test” that represents the truth table of the above expression to confirm it is working.

Save the text output analysis of the truth table as well as the “digital”

file itself. Save these as part_b.txt and part_b.dig, respectively.

Part C

For Part C, build the following truth table using P-channel and N-channel Field Effect Transistors (FETs).  Note these are the same transistors which we described in the lecture as PMOS and NMOS FET transistors:

The FET components can be found under

Components->Switches:

Once you have finished, create an automated test named “part c test” with the above truth table to confirm it is working correctly. Save the text output analysis of the truth table as well as the digital file itself. Save these as part_c.txt and part_c.dig, respectively.

APPENDIX

The XOR gate: It’s really not a complicated gate to understand if you have

fully understood how the AND, OR, NOT gates work. Just like AND, OR, the XOR  gate is a multi-input (>1), single output logic gate. If I were to describe a general n input XOR gate (in1 , in2 , in3 , … ., inn ) with the output signal out, then I’d verbally say: “out is high ONLY if an odd number of inputs are high” .

The following is the truth table for a 2-input XOR gate:

In the above truth table, out is 1 only when one of the inputs (i.e. an odd number) of them is 1.

Likewise, here’s the truth table for a 3-input XOR gate: