Hello, if you have any need, please feel free to consult us, this is my wechat: wx91due
CSCI 2500 —- Computer Organization
Homework 05 —- Due Friday, November 22, 2024
Overview
Homework Specifications
Every student has a RIN number that is specific to themselves. You use your RIN to derive a sequence that is unique to yourself. You use the methods we reviewed in class to design and implement a counter that counts the numbers in this sequence.
The Derived Sequence
RIN = 664355644, then the derived sequence is 6 → 4 → 3 → 5.
MyDesign.txt
The file named MyDesign.txt is used to create the truth table and Karnaugh map to come up with the minimized output functions. You need to use your derived sequence to fill up the truth table. For each current state (A_t B_t C_t D_t) you need to come up with the next state (A_t+1 B_t+1 C_t+1 D_t+1).
If the sequence is 6 → 4 → 3 → 5 then if the current state is 6 (0110), the next state is 4 (0100). If the current state is 4 (0100), the next state is 3 (0011). If the current state is 3 (0011), the next state is 5 (0101). If the current state is 5 (0101), the next state is 6 (0110) again. For the current state values (A_t B_t C_t D_t) that do not have a next state value (A_t+1 B_t+1 C_t+1 D_t+1), you can put don’t cares.
After you are done with the truth table, you fill up the k-maps (one for each output) and make merges to come up with the minimized output functions.
Verilog Code
You must use structural design for this assignment. A general diagram is provided at the end of the MyDesign.txt file that you can review. The behavioral design for Verilog code for this homework leads to zero (0) points for this part of assignment.
You need to design a Reset input that resets your counter to its initial digit. In the previous example it is 6 (0110). If we assign each bit to a DFF, to generate value 6 (0110) after the Reset input is activated, DFF3 should be reset, DFF2 should be set, DFF1 should be set and DFF0 should be reset. That would give us the value 6 (0110) in (DFF3 DFF2 DFF1 DFF0).
OpenCircuits Design
You also need to design the circuit with OpenCicuits. You need to design the layout of your circuit and save your work as hw05.circuit. You are not allowed to use the tool available for this purpose in OpenCircuits. Using that leads to no credit for this part.
Submission Instructions
Before you submit your code (Verilog code), be sure that you have clearly commented your code (this should not be an after-thought). Further, your code should have a clear and logical organization.
You need to follow the following coding conventions:
1. Naming Conventions:
a. Use meaningful names for variables, functions, classes, and other identifiers.b. Follow a consistent naming style, such as camelCase or snake_case.
2. Indentation and Formatting:
a. Use consistent indentation for code blocks, typically using spaces or tabs.b. Format code for readability, including proper spacing around operators and keywords.
3. Comments:
In the EDA playground, you can enable “Download files after run” in the “Tools & Simulators” section on the left side of the screen. This will download your project after you run it. From the .zip file that is downloaded, you only need design.sv and testbench.sv files.a. Add comments to explain complex sections of code or provide context.b. Avoid unnecessary or redundant comments; let the code speak for itself whenever possible.
After you are done with your code, you should also copy the URL link (in the address bar of your browser) of your project (playground) and paste it in MyDesign.txt in EDA Playground URL so that the graders can review your code.
To submit your homework, make a .zip file that contains your design.sv, testbench.sv, hw05.circuit and MyDesign.txt files. The name of this file is Homework05.zip. You submit this file to Submitty to a gradeable called Homework05.