FINAL EXAMINATION
Term 3, 2021
ELEC4602
Microelectronics Design and Technology
QUESTION 1 [25 marks]
Figure 1 shows a layout implemented in the 0.18µm CMOS process described in the information sheet. Process parameters, device equations, layer key and design rules can be found on the information sheet.
(A) Draw the x-x' cross section.
(B) Draw the circuit schematic of the layout, including transistor dimensions and types, and mark the nodes A to F on the schematic.
(C) Find the zero-bias source-bulk capacitance Csb of the transistor whose gate is connected to node C, assuming this transistor is in saturation.
A 4-channel, differential, 10-bit analogue-to-digital converter chip has a core-limited layout and the following pads:
(D) Explain and draw how to arrange the pads on the chip.
The analogue-to-digital converter chip is implemented in the standard 0.18µm CMOS process described in the information sheet which has typical linear MiM capacitors (CArea = 1 fF/µm2 ) and HIPO resistors (R = 1 kΩ/ ) available. For good performance, the chip needs on-chip supply decoupling capacitance of substantial value.
(E) Discuss how to best implement on-chip supply decoupling capacitance on the chip.
QUESTION 2 [25 marks]
Figure 2(a) shows a multiply-by-two circuit which is to be used in an unsigned pipeline analogue-to-digital converter (ADC). The circuit is based around a conventional two-stage operational am-plifier with a source-follower output stage and resistive feedback. The circuit is implemented in the 0.18µm CMOS process described in the information sheet with added low-threshold tran-sistors, and all the NMOS transistors used are of the low-threshold version with Vth0N = 0.2V. Some known circuit parameters are shown in Figure 2(b). Bulk effect and, where appropriate, channel length modulation can be ignored in this question.
In normal operation, 0V ≤ VOut ≤ 1.2V. The effective voltage of M5 must satisfy VEff5 ≤ 0.15V for all output voltages.
(A) Find suitable transistor dimensions (W and L) for M5.
Assuming the transconductance of the differential pair M3,M4 is high, the standard deviation of the random offset error in the amplifier is given by: σOS = K/√ W3L3, where K = 20mV· µm. The amplifier offset must be |VOS| < 4mV in 99.7 % of devices (i.e. 3σOS ≤ 4mV).
(B) Find suitable transistor dimensions (W and L) for M3 and M4.
In the following, it is assumed that W3/L3 = 250. It is further assumed that the operational amplifier’s output resistance is small and that its open-loop gain is given by
where C1 +C2 = 500 fF. The Multiply-by-two circuit must have a phase margin of PM≥ 45◦ .
(C) Find a suitable value for the compensation capacitor, CC.
The operational amplifier output voltage range is limited; in the following, it is assumed that this limitation limits the output voltage range of the multiply-by-two circuit to 50mV ≤VOut ≤ 1.5V.
(D) Discuss the consequences of the limited output voltage range on ADC performance.
(E) Modify the design such that the minimum operational amplifier voltage does not cause issues with ADC operation.
QUESTION 3 [25 marks]
Figure 3 shows a two-way digital multiplexer implemented in the 0.18µm CMOS process de-scribed in the information sheet: signal A0 or signal A1 is directed to the inverted output Y depending on the state of the control signal S. Signals A0, A1 and Y have regular logic levels (VDD = 1.8V and 0 V) while signal S operates at low-voltage logic levels (VDDL and 0 V) neces-sitating the use of a level-shifter as shown in the figure. Simplified digital transistor models may be used in this question.
(A) Choose transistor dimensions for M7-M14 assuming CL is small.
In the following it is assumed that all transistors have dimensions W = 1.2µm, L = 0.3µm, and that CL = 20 fF.
(B) Find the A0-to-Y rising propagation delay when A1 is High.
In the following it is assumed that power dissipation in the multiplexer is caused entirely from the charging of capacitances; it is further assumed that A0 is Low, and A1 is High.
(C) Find the energy delivered from VDD when S has a High-Low transition.
For proper operation of the level-shifter, ron1 > ron2 must be satisfied, where ron1 is the on-resistance of M1 when x1 is at 0V and ron2 is the on-resistance of M2 when S is at VDDL.
(D) Find the minimum allowed value for VDDL, VDDL,min.
(E) Design a 4-way digital multiplexer with low-voltage control signals.