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CS154 Computer Design Lab Lab 2 Sequential Circuit Design

The objective of this lab assignment is to design a sequential circuit. You will submit your specification and your VHDL code through EEE, as in Lab 1.

Please read ALL instructions carefully. Only properly submitted assignments will be graded.

Specification

Your task is to design a 3-bit down counter. The counter is unsigned and counts modulo 8. The initial value after the reset is 7, the next value after the clock is 6, etc.

The design should consist of 2 parts, a combinational circuit that "computes" the next counter value based on the current value (e.g. function F) and a D flip-flop based 3-bit register storing the count.

First, specify the counter logic with a truth table, e.g. Next = F(Current) as in Next and Current state. Write down sum of products expression for F.  Second, draw a diagram connecting F to the register, the reset and clock signals.

Design

Download lab2.zip and unpack it.

The counter module (that is, the lab2 entity) has two 1-bit inputs (clk and reset_N) and one 3-bit output (count). The rising edge of the clock signal decrements the counter to the next value. The reset signal reset_N sets the output of the counter to 7 asynchronously, which means counter value changes to 7 immediately after reset signal arrives, regardless of the clock. Remember, reset_N is an active-low signal.

Your VHDL design should consist of combinational logic implemented using concurrent signal assignments in the architecture body and a register update process.

The top level of your design should be called lab2 and needs to have the following ports (in the same order as given here, with the same names):

Inputs:
clk: std_logic
reset_N: std_logic

Outputs:
count: std_logic_vector (2 downto 0)

Name and order of the ports in your design is important. To receive full credit please follow the order and assign names as above.

Verification Due together with the design.

Your test bench should generate a clock signal. The clock cycle period should be 10 ns.  Verification should be done using assert statements.

Make sure the test is not on the rising edge.

First, verify that the reset signal can reset the counter to 7 asynchronously (reset should last for 2+ clocks). Also verify that the counter would start counting after the reset signal is removed. The reset signal should not change at the same time as the clock`s rising edge.

Second, verify the counting functionality by applying the clock for at least 10 cycles to the counter. You should see all possible output states in your tb.

What you should produce in this lab:

Please submit the specification, including the truth-table, the logic expressions and a block diagram.

Please submit the VHDL design and test-bench.

Demo – in class