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CS154 Computer Design Lab

Lab3 Register File (RF)

The objective of this lab assignment is to design a register file using D flip-flops.

The MIPS register file implements 32 registers, each of which is 32 bits wide. Register number 0 is a zero register: its content is always 0 and it can not be changed. Registers 1 through 31 store any value assigned to them.

There are data, address and control ports to the register file. There should be 3 data ports: 2 for reading and 1 for writing. During each clock cycle, values from 2 registers can be read through the 2 read ports (d_out_1 and d_out_2) and 1 can be written through the write port (d_in). All 3 data ports are 32-bit wide.

The address ports are rd_addr_1, rd_addr_2 and wr_addr. RF addresses are 5bits.

A wr_en control signal is used to write the value on port d_in to a register addressed by wr_addr. The register file also needs a clock signal (port clk). Write operations are synchronized with this clock.

Specification

To help you better understand the RF design draw a block diagram of the register file described above but with only 8 registers. Simplify the drawing by showing a register file with only 3 registers, i.e. show only registers 0, 1, and 7. You can represent the middle registers with ‘…’.  Use a rectangle for representing a single register.

You should use the following building blocks in your block diagram: a 32-bit register (with a write enable), a 32-bit wide MUX, and a 32-bit wide3-8 decoder.  Show bit width with just bus width, i.e. a register is a rectangle with in, out, clk, and wr_en signals.

Show the use of the write enable signal within a register separately. Label each input of the MUX with a control input value that selects the particular input.

Pay attention to the wiring. Label the wires with proper signal names and mark the width.

Design

You will design the register file with 32 registers in your next lab (Lab4).  There will be no separate entity for the RF (although you may do one for practice purposes using the template VHDL files provided. The interface, e.g. ports, is already defined. You need to add code for functionality. Do not make any changes to the interface).

You will use an array of std_logic_vector to implement the register file.  This implementation should consist of a register file writing process and 2 concurrent signal assignments to read the two registers specified (more on this below).

Using an array to implement the register file automatically includes the decoder and the mux component to address a specific register by the array reference. Please refer to lecture slides (Slide #5 and #6 of Lecture 5). The register file declaration should be something like:

RegFile: array (0 to 31) of std_logic_vector(31 downto 0);

The declaration in the slides has many named subtypes and constants. Some of them are useful in other labs and it will be a good idea to keep the declarations in a separate package for future labs.

Index to an array elements must be of type "INTEGER". Convert a signal of type STD_LOGIC_VECTOR to integer using the VHDL function "TO_INTEGER()". It is declared in "IEEE.NUMERIC_STD" package, which you need to include. The argument of this function should be either STD_LOGIC_UNSIGNED or STD_LOGIC_SIGNED. So you need to first cast the STD_LOGIC_VECTOR to STD_LOGIC_UNSIGNED, then pass it to TO_INTEGER().

The following example uses wr_addr as the array index:

RegFile( TO_INTEGER ( UNSIGNED(wr_addr) ) );

You should use a process to implement the write operation. Think about which signals should be in the sensitivity list. Pay special attention to R0: when wr_addr = "00000", an update should not happen.

Verification - with Lab4 verification.

Normally, one would need to test a memory or a register file as described below.  But you do not need to do this.

Addressing:

To make sure that you are reading from / writing to a specific register you want. All addresses and data ports need to be tested. This has to be done first, because the following tests will test each register and to do that you must make sure you are able to access each register.
You should write unique values to different registers, and read from them and see if what you read is what you have written.

Content (not required):

To make sure that each register holds what was actually written. No "stuck at" errors exist. Each bit in each register must be tested.
One can write "000...0" and "111...1" to each register and read from them and see if what you read is what you have written.

All input signals in test bench should be 1 clock long and go high a short time after a rising clock edge. Use the assert statement and expected values to detect errors.

What you should produce in this lab:

A block diagram of the register file you designed that has 8 registers (a scanned readable drawing is fine).

Please submit via Canvas.