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CS250A Computer Systems Architecture Homework 1.
1. Integer pipeline (Fig. 2.3). Assume that registers are written in the 1st half of the clock cycle, read in the 2nd half.
Show cycle by cycle execution of the following code segment. Identify every possible type of hazard, mark the hazards by arrows.
The processor does not use forwarding, resolve all hazards by stalling. Shows stalls with a letter "S" in an appropriate cycle.
Execute all instructions shown after the branch is resolved.
Instr/Clock Cycle 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 ...
Xor R4, R5, R9 F D X M W
Add R1, R1, #4
Sub R6, R5, R4
BNE R1, R3, L_
Ld R5, 52(R6)
St R5, 8(R4)
Sub R7, R5, R4
Add R2, R2, R3
...
L:
2.
Same as problem 1, but now the processor supports forwarding on data hazards. Show the cycle by cycle execution.
3.
Start with the solution to problem 2 and reorder instructions to reduce the remaining stalls. Show the new code and its cycle by cycle execution.
4.
Assume that we modified the MIPS ISA to only have BZ (branch on equal zero) and BNZ (branch not equal) conditional branches.
They use one input register (see below) and the comparison with zero is faster than comparing two registers in the BNE/BEQ instructions.
Can you modify the architecture to take advantage of this? (state any additional, but reasonable assumptions you made).
BZ R1, L
5.
Assume that we added a Branch Target Buffer in the IF stage together with the BHT (array of counters). The BTB has a 20% miss rate and a 90% prediction accuracy. What is the effect of branches on the CPI of the modified processor?