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EGEC 540
Computer Arithmetic Structures
Fall 2023
Exercise 2
(Due via Canvas by 11:45 PM on October 26, 2023
1. Design the Moore finite state machine for a serialadder and sketch the block-level logic diagram for a 4-bit serialadder.
2. Find the overall worst-case delay (e. the delay at which all the outputs of the circuit are finalized) for each of the unsigned adder circuits mentioned below (carry-in to the first bit position=0 in each case). Assume that the delay due to one level of gates is D. Also, assume that inverted versions of signal variables are already available (i.e. ignore inverter delays). Furthermore, assume unlimited fan-in unless specified otherwise.
I. 8-bit ripple-carry adder (RCA)
II. 8-bit global carry-lookahead adder (GCLA)
III. 8-bit global CLA (GCLA) assuming fan-in limit of 4 IV. 8-bit global CLA (GCLA) assuming fan-in limit of 8 V. 8-bit carry-completion adder (CCA)
3. Find the overall worst-case delay (e. the delay at which all the outputs of the circuit are finalized) for each of the unsigned adder circuits mentioned below (carry-in to the first bit position=0 in each case). Assume that the delay due to one level of gates is D. Also, assume that inverted versions of signal
variables are already available (i.e. ignore inverter delays). Furthermore, assume unlimited fan-in unless specified otherwise.
I. 16-bit block CLA (BCLA) with block size=8
II. 16-bit block CLA (BCLA) with block size=4
III. 16-bit block RCA-BCL adder with block size=8 IV. 16-bit block RCA-BCL adder with block size=4
V. 16-bit block carry-skip adder (CSA) with block size=2
VI. 16-bit block carry-select adder (CSelA) with block size=4. Assume that the first block is implemented as an RCA
4. For the unsigned addition of the given bit-pattern pair, identify the overall delay (e. the delay at which all the outputs of the circuit are finalized) experienced in the case of each unsigned adder circuit mentioned below (carry-in to the first bit position=0 in each case). Assume that the delay due to one level of gates is D. Also, assume that inverted versions of signal variables are already available (i.e. ignore inverter delays). Furthermore, assume unlimited fan-in.
0 0 1 0 1 0 1 0 0 1 1 0 1 1 1 0
1 1 0 0 1 0 1 1 1 0 1 0 0 0 1 1
I. RCA
II. CCA
III. BCLA with block size=8
IV. RCA-BCL adder with block size=8
V. CSA with block size=2
VI. CSelA with block size=8. Assume that the first block is implemented as an RCA
5. For each of the signed adder/subtractor circuits mentioned below, find the overall worst-case delay (e. the delay at which all the outputs of the circuit are finalized). Assume that the core unsigned adder is implemented using RCA logic in each case. Assume that the delay due to one level of gates is D. Also, assume that inverted versions of signal variables are already available (i.e. ignore inverter delays).
Furthermore, assume unlimited fan-in.
I. 8-bit 1’s complement adder/subtractor
II. 8-bit 2’s complement adder/subtractor