Hello, if you have any need, please feel free to consult us, this is my wechat: wx91due
XJEL2665 Semester 2 Project Brief
(May 2025)
Two-mode Timer
Introduction
After diving deep into Semester 2, I hope you have all gained a solid grasp of FPGA and hands-on experience with coding the FPGA board. Now, it is time to put that knowledge to the test with our final assessment!
You will be challenged to create a Two-mode Timer using Verilog and FPGA, further shaping your skills to the next level. In Mode A, it will function as a stopwatch that run on 100 Hz clock up to 99 seconds and 99 cent-seconds. In Mode B, it will perform as a timer that run on 1 Hz clock and counting down from 2:00 minutes.
In this briefing document, you will find the basic design requirements and a template Quartus project will be given to kickstart your design. From there, it is up to you to innovate and build new modules to achieve as much functionality as possible you would like within the assessment period.
Alongside your practical work submission, you will submit a short validation report (template provided) and a demo video (.MP4 format!) showcasing your code and final implementation on the DE10-lite board.
Get ready to unleash your creativity and technical prowess! Let's make this project a success!
Block Diagram
Here is the Block Diagram to illustrate the baseline structure of the Stopwatch.
|
Warning of Using AI tools! This assessment is category as “AMBER” according to the University AI traffic light guideline. This means that you are PERNUTTED to use Gen AI tools, but only for the specific purpose(s) identified. Gen AI tools CAN be used in an assistive role for this assignment: · Obtain GENERAL knowledge about Verilog code syntax. -Example question: How to concatenate the two arrays in Verilog? · Seek advice for debugging error code. -Example question: What does the error code 335093 in Quartus mean? · Seek clarification of how the module works. -Example question: How does clock divider works? · Learn how to produce video or transfer the video format. -Example question: How to transfer MOV format to MP4 format on Mac OS? Gen AI tools CANNOT be used for this assignment:
· Writing the Verilog code, testbench code or any other part for your practical submission. -Example question: Write a Verilog code for programme counter. · Write or re-wire/re-phrase the script for your report/presentation. -Example question: Generate a script to discuss clock divider. · Use AI to generate based code to modify! This is because the AI tools are bad to show various different way of coding and coding, like writing, it something very personalised, especially at the entry level. · Debugging code using AI directly. Please note: the Verilog code generated by several different AI tools has been included them in the originality check database. A copy or minor modification will discredit your performance and will potentially invoke an academic malpractice investigation! If you disregard these instructions and use Gen AI for any purpose beyond those permitted, you risk being accused of academic misconduct. The use of Gen AI must be acknowledged in an ‘Acknowledgements’ section of any piece of academic work where it has been used as a functional tool to assist in the process of creating academic work. If it is suspected that you have used a Gen AI tool to produce part of your work, but you have not acknowledged this use, this could be investigated under the Academic Misconduct procedure. The minimum requirement to include in acknowledgement: · Name and version of the generative AI system used e.g. ChatGPT-4.0 · Publisher (company that made the AI system) e.g. OpenAI. · URL of the AI system · Brief description (single sentence) of context in which the tool was used. For example: “I acknowledge the use of ChatGPT-3.5 (Open AI, https://chat.openai.com/) to summarise my initial notes and to proofread my final draft.” |
|
|
Design Rules
This section summarised the rules you MUST follow in the assessment.
• Please do NOT modify the existing document headers (you can change the parameter type but do not change the parameter name or delete any). You are allowed to add new input/output if you want to implement additional functions.
• You need to pair ALL modules in your project with a testbench and validate your module with the testbench! (Note: You should NOT use auto generating function and it will be regarded as academic malpractice!)
• Please read the Report Template before coding the project. There are several additional requirements towards your code design and information or figures you need to prepare for the report.
• Follow the block diagram as a guide for the top-level design and the interconnection between submodules. Please note, those submodule in solid box are compulsory while those in dashed line are optional. This diagram acts as a fundamental requirement for your project. You are encouraged to expand the function by adding your modules/functions on top of it.
• I expect you to follow the design practices that have been covered this year and will use them to assess your submission. Hence you should try to maximise the use of structural logic via primitive logic modules (or in other words, the knowledge we learnt before Unit 4.3). I understand this is challenging so it is okay to use behavioural if, Case statements you learnt from Unit 4.4. But you should NOT over-rely on the behavioural logic! And doing so will affect your final mark dramatically regardless your overall completeness!
• When we test your design, we will toggle (re)set and examine the functionality after that point – you will not be judged on anything that happens in between T0 and the reset signal.
Project Submission
This section summarised the requirements you MUST follow in the assessment submission.
The submission deadline is:
2:00 pm UK time on 14th May 2025
Note: As per the Code of Practice on Assessment, a late submission penalty of 5% per day will be applied if your missed the deadline! And an enhance rule will be applied to this assessment due to the high weight (50%). You MUST gain at least 30% in this assessment to pass the module on top of the normal 40% passing rule.
Practical Submission
When you are ready to submit, compress your WHOLE project folder (into a .zip file only!) and submit it via the link on Minerva. Ensure that you have included ALL of your submodule files, test benches as well the sub-folders in the project folder.
Report Submission
A Report Template will be provided to you to guide your report writing. You will be asked to provide evidence to prove your ability to simulate and validate your code in ModelSim. You should finish each session fully and to the best of your ability. In each session, a detailed requirement is listed. Please make sure you read them carefully and cover all the contents asked.
The reports are to be submitted via Turnitin at the same time as your practical work.
Presentation Submission
Like the Unit 2 assessment, you also need to prepare a video presentation (MP4 format! And around 10 mins, not exceeding 12mins) to demonstrate your practical work design and submit it via the submission portal on Minerva. You should include the following contents in your presentation:
• A quick introduction of the practical work and explain the function briefly.
• Module by module, spend several slides to explain your project design.
You can use the RTL viewer image/flow chart to support your discussion. Of course, showing code is also a good idea but your need to make sure you conduct discussion accordingly.
• A video demonstration to show you coding running on the DE10-lite FPGA board.
• A short self-reflection on the project covering the topics below:
o What part of the project are you most proud of in your design? For example, achieving additional functions or parts you think your design works most successfully.
o Which part do you think is most challenging and how do you deal with this?
o If you have more time, what function do you want to develop? And how long do you think you need to finish them?
Please make sure you are not reading scrips in the video and also you need to show your face along the presentation (using Teams recording or PowerPoint Cameo).
System Design Guideline
This section summarised the detailed design requirement you MUST follow.
There are seven (or eight depend on your design) main sub-modules and one top-level design should be implemented in this project:
Clock Divider – A clock divider that takes in a 50 MHz clock signal generated by the MAX10 board and divides it down to 100 Hz and 1 Hz to drive the Timer Core Logic. Please refer to the Unit 4.3 screencasts for some design ideas.
Timer Core Logic – The main logic controller for the Two-mode Timer, handling the counting behaviour and start/stop/reset functions. You MUST construct the Timer Core Logic based on two Program Counter submodule.
Program Counter –This Program Counter do the similar thing as you learnt last semester. It will perform counting behaviour by default. It can also set to certain counting value when the load pin active and reset to the initial value when the reset pin is activated.
Reverser – One of the running modes will require the number counting down. So, you need to use this module to covert a counting up value from Timer Core Logic to counting down value.
Two-mode Timer – The full system’s top-level design, organised as shown in the block diagram.
Mode Configuration* – This module is used to generate different parameter configuration for the two different running mode. *Note: you can merge this module into the top-level design depends on your design.
Binary to Seven Segment Encoder* – An encoder that takes the binary numbers and converts them to a format appropriate for display on four seven-segment displays. *Note: you can construct this by using two submodules instead, i.e. Binary to BCD Encoder and BCD to 7-Seg Display Module.
Module Specifications
|
Clock Divider |
|
|
ClockDivider |
|
|
Inputs |
|
|
CLK_50MHz |
A 50MHz clock signal from FPGA |
|
rst_n |
An active-low set signal |
|
Output |
|
|
CLK_100Hz |
A 100Hz clock signal |
|
CLK_1Hz |
A 1Hz clock signal |
|
Function |
|
|
This module will divide the 50MHz input clock into a 100 Hz and 1 Hz output clock, which will give a clock signal with a period of around 10ms and 1s to drive other modules.
The reset will reset and hold the output clock value to 0 when the reset signal is LOW. |
|
|
Timer Core Logic |
|
|
TimerCoreLogic |
|
|
Inputs |
|
|
Edit your own parameter(s) |
Configuration parameters signal(s) for two modes |
|
clk |
Clock signal (either 100 Hz or 1 Hz) |
|
rst_n |
An active-low signal to reset the module |
|
StartStop |
A control signal to start (active) and stop (pause) the module |
|
Output |
|
|
[7:0] LSBbinaryout |
The LSB output signal in binary |
|
[7:0] MSBbinaryout |
The MSB output signal binary |
|
Function |
|
|
Note: The Mode Selection signal does NOT operate the Timer Core Logic. It will only run based on certain configuration parameters
A falling edge on the reset input (rst_n) should freeze the timer and reconfigure the Timer to the default output state. i.e. in Mode A, the Two-mode Timer should show 00.00 on 7-Seg display; In Mode B, the display should be 02.00.
Hint: due the Reverser module, the value sent out may not be 2 and 0 in MSB and LSB when the Two-Mode Timer is configured in Mode B!
After reset the module, the Start/Stop signal (StartStop) will active the counting by trigger it once, and pause the counting by trigger it again. It will loop between Start and Stop behaviour in follow activation.
Hint: If you cannot work out the Start/Stop function as described, you can use the switch to control StartStop, i.e. signal HIGH: Start; signal LOW: Stop.
|
|
|
Program Counter (PC) |
|
|
|
ProgramCounter |
||
|
Inputs |
||
|
clk |
Clock signal (either 100 Hz or 1 Hz) |
|
|
[7:0] ResetVal |
Input value to update the PC when reset is active |
|
|
[7:0] LoadVal |
Input value to update the PC when load is active |
|
|
reset |
An active-high signal to reset the PC |
|
|
load |
An active-high signal to load value in the PC |
|
|
inc |
An active-high signal to start the counting |
|
|
Output |
||
|
[7:0] PCoutput |
The PC output signal in binary |
|
|
Function |
|
|
|
Note: You MUST build the Timer Core Logic using this module!
The function of the PC module is slightly modified from what you learnt from last semester (Unit 1.3). When reset, instead of resetting to 0, it will be reset to certain value specified by RestVal signal. All the other function maintains the same.
Hint: although similar in function, the load needs to wait the clock signal (clk) to trigger while reset will be action immediately when triggered. So, use the two signals wisely as they are doing different job in this Timer Core Logic module. |
||
|
Reverser |
|
|
|
Reverser |
||
|
Inputs |
||
|
[7:0] RevIn |
The 8-bits BCD value input |
|
|
ModeSel |
Signal to control the module output |
|
|
Output |
||
|
[7:0] RevOut |
The 8-bits BCD value output |
|
|
Function |
|
|
|
This module will modify the input binary signal to change the counting behaviour. When ModeSel is LOW, the RevOut = RevIn and the Two-mode Timer will count upwards. On the contrary, when ModeSel is HIGH, the output will be reversed, and the Two-mode Timer will count downwards.
In other words, when ModeSel is HIGH, the input value following 1 ,2 ,3…7, 8 will be modified to 8, 7, 6…2, 1 (this is example to illustrate the functionality of the reverser, your module do not need to follow this design).
Hint: I would expect you use method you learnt from Unit 4.2 to construct this module. However, other method is also acceptable (but your need to justify the benefits)
|
||
|
Binary to Seven Segment Encoder |
|
|
SevenSegEncoder |
|
|
Inputs |
|
|
[7:0] LSBbinary |
The LSB binary value input to display |
|
[7:0] MSBbinary |
The MSB binary value input to display |
|
ModeSel |
Signal to control the internal Reverser |
|
Output |
|
|
[6:0] HexMSBH |
7-Seg display signal for higher digit in MSB |
|
[6:0] HexMSBL |
7-Seg display signal for lower digit in MSB |
|
[6:0] HexLSBH |
7-Seg display signal for higher digit in LSB |
|
[6:0] HexLSBL |
7-Seg display signal for lower digit in LSB |
|
Function |
|
|
Like what you learnt in Unit 4.2, this module should take a binary input and encode these in a format appropriate for two seven-segment displays. However, you will need to embed a Reverser module inside so the final display can go up/down regardless the input can only go upwards.
Hint: since the code given is based on 8 bits binary so it will be a 2^8 LUT if you following the method mentioned in Unit 4.3. Hence you may need to use other method to convert them into BCD. The proper mathematics method is called double-dabble. You can choose to use this approach or another pure math calculation method. Although it is not recommended if you need to do similar thing in your future career since this approach will waste a lot of FPGA/MCU computational power!
|
|
|
Two-mode Timer |
|
|
MainCode |
|
|
Inputs |
|
|
CLK_50MHz |
A 50MHz clock signal from FPGA |
|
rst_n |
An active-low signal to reset the module |
|
StartStop |
A control signal to start (active) and stop (pause) the module |
|
ModeSel |
Control signal to switch between the two modes |
|
Output |
|
|
[6:0] HexMSBH |
7-Seg display signal for higher digit in MSB |
|
[6:0] HexMSBL |
7-Seg display signal for lower digit in MSB |
|
[6:0] HexLSBH |
7-Seg display signal for higher digit in LSB |
|
[6:0] HexLSBL |
7-Seg display signal for lower digit in LSB |
|
DOT |
The flashing singal at the MSB lower digit 7-Seg decimal LED to indicate the clock signal |
|
Function |
|
|
This module should be set as the top-level design for the project as illustrated in the block diagram.
A falling edge on the reset input (rst_n) should freeze the timer and reconfigure the Timer to the default output state. I.e in Mode A, the Two-Mode Timer should show 00.00 on 7-Seg display; In Mode B, the display should be 02.00.
The Start/Stop signal (StartStop) will active the counting by trigger it once and pause the counting by trigger it again. It will loop between Start and Stop behaviour in follow activation.
Hint: If you cannot implement the Start/Stop function as described, you can use the switch to control StartStop, i.e. signal HIGH: Start; signal LOW: Stop.
The ModeSel signal will swich between Mode A: a stopwatch that run on 100 Hz clock up to 99 seconds and 99 cent-seconds; and Mode B: a timer that run on 1 Hz clock and counting down from 2 minutes. Note: When implement the module, I would NOT mind if your stopwatch/timer loop back to initial state once reaching maximum count (99:99) or countdown to 00:00. But it is still good if you can implement an auto freeze function once the stopwatch/timer reached the boundary. The input and output signal should be connected to the following pins:
Inputs CLK_50MHZ: MAX10_CLK1_50 rst_n: KEY0 StartStop: KEY1 Outputs SevenSegMSBH: HEX3 [0-6] SevenSegMSBL: HEX2 [0-6] SevenSegLSBH: HEX1 [0-6] SevenSegLSBL: HEX0 [0-6] DOT: HEX2 [7] You can add additional functions and additional inputs/outputs to the project and create relevant submodules to achieve relevant functions. |
|