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ELEC4602 Lab 2 Report
Oct 8th, 2024
Introduction
Lab 2 involved the introduction of the circuit and schematic editor within the Cadence program. For the development of the use of these tools, a circuit schematic of theNAND gate was developed and then a test bench was built for us to validate the operation of our developed NAND gate. For the validation of the circuit, several simulations were performed, including: a transient simulation, DC simulation and an AC simulation. Finally, we were required to confirm that the layout and schematic were matching.
NAND Gate Schematic
Figure 1 NAND Gate Schematic
Figure 1 showcases the circuit schematic created using Cadence Schematic Editor. For the PMOS and NMOS, the VTG cells were used, and their widths adjusted accordingly. PMOS required a width of 120 nm and NMOS required a width of 90 nm. PMOS has its bulk connected to the Vdd and NMOS has its bulk connected to the GND. Vdd and GND were supply nets which were added similarly. Using the wire tool, the MOS and supplies are connected according to NAND circuit diagram. The Pin tool was used to create the input and output ports, where the direction was specified within the properties, i.e. A and B were set to input and Out was set to output.
Test Bench Schematic
Figure 2 Test Bench Schematic
For us to validate the NAND gate circuit that we have developed, we require a test bench to examine the behaviour of our circuit and verify it matches our expectations. In figure 2, the test bench developed within lab 2 can be observed. Using our knowledge learnt from editing a schematic for the NAND gate, similar practices were then used to create the test bench. Where supply nets, wires and instances were utilised. For the supply source, aDC voltage source instance was used, whereas for the gate input sources, voltage pulse sources were used. A capacitor is also connected to the output of the NAND gate for us to observe a smoother output waveform. Also, something to note about the test bench schematic, the inputs for the gate are not “completely wired”, rather wire names were used to connect them since wires which share wire names are automatically connected. Something similar could have been done for the ground wire for a cleaner looking schematic.
When we created the NAND gate schematic, we saved it to our library “lib4602”, which we can use to insert theNAND4602 instance into our test bench schematic.
Figure 3 NAND Gate Symbol
Cadence has a symbol editor which we can use to create neat symbols for our developed components. As seen in figure 3, the traditional NAND gate symbol was drawn.
Transient Simulation
A transient simulation allows for us to observe the voltage and current values at various points on a plot where time is the independent variable. Cadence has a simulation tool ADE Explorer where we can simulate circuits under a “Maestro” tab.
For us, we desired the voltage values of Input A, Input B, and the Output. Within the maestro tab, we need to specify the nodes which we are probing, those being the ones discussed above, and the analysis type we want to use. Using the transient analysis output, the output plot can be seen in figure 4. Where input A is green, input B is purple, and output is red.
The plotted waveform for the output of the schematic follows the expected logic operation for a NAND gate. As seen in table 4, we ignore the delays for now and assume instant operation.
|
Time (ns) |
Input A |
Input B |
Output |
|
0 < t < 0.3 |
1 |
1 |
0 |
|
0.3 < t < 0.55 |
0 |
1 |
1 |
|
0.55 < t < 0.8 |
1 |
0 |
1 |
|
0.8 < t < 1 |
0 |
0 |
1 |
Figure 4 Simulated Output Table
Figure 5 Transient Simulation Output Plot
Another key feature we need to discuss is the propagation delay of the gate. Where propagation delay, tpd, can betaken as the time difference between which the input reaches a desired value, and the output stabilise to the desired output value. Using a slice of the plot, from 1 ns < t < 1.2 ns, we can estimate the propagation delay.