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Summer 2024 CSE100 Homework 3
Due July 24th, 2024
Question 1
Implement the following arithmetic expressions in minimum ΣoΠ (sum of products). Simplify your expressions using Boolean Algebra laws and identities.
a. Y0 = (A4A3A2A1A0 == 110012)
b. Y0 = (A3A2A1A0 > 01012) (unsigned constant greater than)
c. Y0 = (A1A0 ≥ B1B0) (unsigned variable greater than or equal to)
d. Y2Y1Y0 = (A2A1A0 << B1B0) (variable shift left)
Question 2
Design a counter that counts up from 0 to 4. When the counter equals 4, it should pause until the active-low syncronous reset is activated.
a. Draw a schematic of your counter. To simplify your schematic, you may use busses and any higher-level combinational logic cells discussed in lecture.
b. Complete the following waveform assuming 0 clk-to-q, and negative hold time.
Question 3
The following schematic has the MUXes and Flip-flops requried for a 4-word shift register.
a. Show how to complete the 4-word shift register so that it will operate according to the table shown in the following table.
b. Using the following delays, calculate the maximum clock frequency for the 4-word shift register. Now calculate the maximum clock frequency assuming the circuit was expanded to a 512-word shift register.
• MUX4 delay = 300ps
• Flip-flop clk-2-q delay = 150ps
• Flip-flop setup time = 200ps
• Flip-flop hold time = -50ps
Question 4
There are many types of memory in digital design. Some are slow but high density, some are fast but high power. Flip-flops are often used in extremely fast, but area-inefficient volatile storage arrays such as register files. Provided to you is a circuit implementing a register file with four 4-bit registers. We call this a 4-wide 4-bit register file because the 4 registers, (R0 , R1 , R2 , and R3 ) have 4-bits each. Suppose you want to analyze the register file to ensure it meets your design’s timing requirements. Note that the words “registers” and “flip-flops” are used interchangeably in this question.
Figure 1: Register file with four 4-bit registers https://www.ece.mcmaster.ca/~shirani/2di4/lab5
a. Show how the “2 to 4 line decoder” can be constructed by cascading three “1 to 2 line decoders.”
b. Assume the delay of a single “1 to 2 line decoder” is 105ps. Find the equation for the delay of a “log2 n to n line decoder” designed by cascading “1 to 2 line decoders.”
c. Show how the “4:1 MUX” can be constructed by cascading three “2:1 MUXes.”
d. Assume the delay of a single “2:1 MUX” is 125ps. Find the equation for the delay of a “n:1 MUX” designed by cascading “2:1 MUXes.”
e. Next, assume you want to expand the 4-wide 4-bit register file into an n-wide 4-bit register file. Find the maximum operating frequency of the register file in GHz in terms of n assuming a flip-flop setup-time of 150ps (for both D and En), a clk-to-q delay of 250ps, and a hold-time of 100ps. Be sure to use your calculated delay for your “log2 n to n line decoder” and “n:1 MUX”.
To simplify your analysis, assume that all the inputs (“data in”, “write register select”, “write enable”, and “read register select”) are outputted from a flip-flop with 0 clk-to-q delay, and the output (“data out”) is inputted to a flip-flop with 0 setup time.
To create a formula for maximum operating frequency, you will have to use a piecewise function that is comprised of the delay to write to the register file and the delay to read from the register file. The full register file frequency is bounded by which of the two operations takes the longest.
f. Using your formula for maximum operating frequency, how wide can you make your n-wide register file assuming that it’s operating frequency should be capable of 1GHz.
Question 5
Assume you are trying to improve a design’s 32-bit adder. You have access to an effectively infinite number of D-flip-flops, but you only have four 8-bit adders. The existing 32-bit adder has a 2 cycle latency: on the first clock pulse, the inputs A[31:0] and B[31:0] are sent through an array of D-flip-flops and into the four 8-bit adders; on the second clock pulse, the sum is sent through another array of D-flip-flops. Assume that each 8-bit adder has a delay of 20 ns, and each D-flip-flop has a setup-time of 5ns, a clk-to-q delay of 10ns, and a hold-time of 20ns.
Figure 2: Adder between 2 arrays of D-flip-flops
a. Finish the circuit diagram in Figure 2 of the 32-bit adder with a 2-cycle latency by connecting the four 8-bit adders and the D-flip-flops together.
b. What is the total delay after a clock edge until the input to the next D-flip-flop is valid.
c. What is the maximum frequency that this design can be run at?
d. You realize that this maximum frequency is too low, so you decide to pipeline the computation. Now, every 8-bit adder is buffered between an array of flip -flops. Finish the circuit diagram in Figure 3 to demonstrate how the addition can be split across 3 more clock cycles.
e. Verify that your flip-flop hold time satisfied. If hold time is not satisfied, insert additional 6ns buffers until the hold time is met.
f. What is the maximum frequency that this pipelined design can run at?
g. For the pipelined design, after a reset sequence (that invalidates the contents of all flip-flops), assume a new adder input is received every cycle. How many valid 32-bit additions will have finished after 5 cycles, 10 cycles, and 1000 cycles?
Figure 3: Pipelined adder design