Architecture: Assessed Coursework I

The processor P1 takes 16-bit instructions. Bits 0-3 are the opcode, bits 4-5 indicate a register in a

register file, and the remaining 10 bits are used as address or data. The architecture of P1 is shown

below. The registers PC, IR, MDR, A1 and A2 retain their value unless their “write” input is 1. When

“ALU control” is 1, the ALU performs A1+A2; otherwise, it performs A1-A2. The register file and the

memory have separate control signals for reading and writing. The “index” input of the register file    selects a register. In your answers, control signal should either be set to 0 or to 1. Setting any control signal to “X” will be considered incorrect.

(a)  The "load" instruction for P1 takes 3 cycles. In cycle 1, PC is incremented and the instruction is fetched to IR. In cycle 2, bits 6-15 from IR is extended by UX to be a 16-bit address for the  memory, and the content from this address is stored in MDR. In cycle 3, the value in MDR is  stored in a register in the register file. What are the values of the control signals C1, C2, C3, Mread, Mwrite, Rread, Rwrite  etc in each cycle for the “ load” instruction? (25 Points)

(b)  The “sub” instruction for P1 subtracts a value in the memory from the value of a register.

The memory address is given by the 10 bits in the instruction. The result is stored back to the register. How many cycles does the “sub” instruction take? What are the values of the control signals in each cycle? (25 Points)

You should answer the two questions by submitting two CSV files namely “q1a.csv” and “q1b.csv” . A template CSV file is provided with this question sheet in the “data file” section. The CSV file can be edited with a spreadsheet processor or a text editor. Please remove unnecessary rows before submission. For example, if your design takes 4 cycles, please remove the rows corresponding to cycle 5 — 10.

Question 2 (50 Points, one file to submit)

The FunnyCore processor has sixteen 32-bit registers. The processor supports the following instructions:

Note that FunnyCore also supports memory instructions, but these instructions are not listed above

because the memory chip is malfunctioning currently. In this table, “d”, “a”, and “ b” are register

identifiers ranging from 0 to 15, specified as decimal numbers; r[k] represents the content of

Register k. Additionally, here is some additional information on the “ li”, “jz”, and “jp” instructions:

.     In the “li” instruction, i is an immediate value in the format of a 16-bit signed integer. It

should be specified as a decimal integer in the range -32768..+32767 in the assembly code. This number will be automatically sign-extended before it is loaded into the register.

.     In the conditional jumping instructions “jz” and “jp”, the immediate value i is a signed integer. The jump goes forward if i is positive, and backward if i is negative.

For example, the following piece of code adds up all integers in 1..100, and stores the result in Register 0:

Regarding instruction execution, FunnyCore has the following properties:

.    The execution of a “jz” or “jp” or “mul” instruction takes 3 clock cycles; an instruction other than these three only takes 1 clock cycle.

.    A numeric overflow or a jump to undefined code will crash the system immediately.