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CS250A Computer Systems Architecture  Assignment 2

For all problems assume the address is 32bits.  State any (reasonable) additional assumptions you think you need to solve a given problem (although most of the time you should not need any).

Problem 1

a) What are the sizes of tag, index, and offset fields (in bits) for a cache of size S Kbytes, a block size of B bytes, and W-way associativity?

b) A 64KB cache has 32B blocks.  What is the associativity of this cache if the tag size is 18bits?

Problem 2

What is the L2 hit time at which adding an L2 cache to the hierarchy is not profitable, given that an average L2 miss rate is X?

Problem 3

Draw a detailed block diagram of a 24KB, 3-way set-associative cache with 32B blocks.  Show the size and widths of all fields in SRAMs.

Problem 4

a) X% of the lines in a write-back, write-allocate L1 cache are modified.  What is the average memory latency (AML)  in this case, assuming one level of cache? A write-back has to be completed before miss service can start. The average miss rate is over both reads and writes in this case.

b) What is the effect of this cache on the CPI?

Problem 5

A TLB is added to the L1 cache. The page size is 4KB, the cache size 16KB, and the block size is 32B. What is the smallest cache associativity at which the TLB and the cache access can be overlapped.