CIT 5930 Module 03 HW: Transistors to Logic

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CIT 5930 Module 03 HW: Transistors to Logic

Due Date: Monday 9/16 @11:59pm via gradescope.com

Which Lectures Should I Watch to Complete this Assignment?: Modules03 

Video lectures can be found on canvas under “Class Recordings”

PDF files of the module lectures can be found on canvas under “Files->Module_Slides”

What textbook sections should I read to complete this assignment? 3.1-3.3

From the course textbook, “Intro to Computing Systems” by Patt & Patel

Part 1) Transistors & Gates (reading: 3.1-3.2)

From the textbook: 3.1, 3.2, 3.4, 3.5, 3.6*, 3.7, 3.8*, 3.11

* For 3.6, draw the interconnected logic gates that the transistors are implementing – Make certain your truth table still works when you are done!

** In the international edition of text, function is wrong use: Y=NOT(A AND (B OR C)) 

Custom Problem #1 (logic down to transistors):

Given the Logic Function: Y= (B OR C) AND (C AND A)
(a) Implement this function at the gate level (AND gates, OR gates, Inverter gates) without the use of a PLA or reduction.
(b) If AND gates have a delay of 1.5ns, OR gates have a delay of 2ns, and Inverters have a delay of 0.5ns, what is the total delay of your circuit?
(c) Implement your gate level circuit from (a) in CMOS (i.e. – transistors)
(d) Generate a truth table for your function (rows of table must be in numerical order)
Part 2) Combinational Logic Circuits (reading: 3.3)
From the book: 3.12, 3.13, 3.14, 3.15, 3.16, 3.22, 3.23, 3.25, 3.28

Custom Problem #2 (PLA vs. Boolean Algebra):

(a) In Custom Problem #1, you implemented a Boolean Function. Now, use the truth table you generated in part (d) and implement it using a PLA without reduction.
(b) Assuming the same gate delays as Custom Problem #1, what is the gate delay of your PLA implementation
(c) Which implementation in terms of speed?
(d) Which implementation is better in terms of area on an integrated circuit?
(e) E.C. 2-points – If possible, reduce this logic function using Boolen Algebra, explain all reduction steps you use.
Custom Problem #3 (Multiple Output PLAs)

Using the lecture notes, locate the “Full Adder circuit” truth table with inputs A, B, C and outputs S and C-out.

(a) Implement the full adder using a PLA
(b) E.C. 2-points – You can you implement a full adder using fewer gates than the PLA. Show a simpler implementation than the PLA, and explain in detail how you arrived at your design.CIT 5930 Module 03 HW: Transistors to Logic
Extra Credit (Boolean Algebra Brain Teasers!)
(1 point each) Use Boolean algebra to prove the following identities. Make sure to show your simplification steps and label each Boolean identity/law you use. Note: “+” is short for OR, multiplication is short for AND.
(A + B) + (AB) = 1
(AB) + (AB) + (AB) = (A + B)
(A + B)(A + B) = A
A + AB = A + B
(A + B + C)(A + BC) = A + B'C
Directions on how to submit your work: You are encouraged to do all this homework with pencil/paper first and keep a copy of it. To submit your work, you must first convert your handwritten work to a PDF (using an actual scanner or a photo to PDF converting app – “GeniusScan” is free and is my favorite), then navigate to canvas, click on the “Assignments” -> Mod03_HW->Load Mod03_HW in a new window. This will bring you to a system called: Gradescope. It will allow you to upload your PDF and it will ask you to “select/identify” the parts of your HW that correspond to the different problem #s in the assignment. Sometimes it is easiest if you do one problem per PDF page, either way you choose, make your handwriting very clear, so we can grade your work well.

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