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CS154 Computer Design Lab
Lab 7: Datapath Synthesis and Gate-level simulation 

Please read ALL instructions carefully. Only properly submitted assignments will be graded. Make sure to create a zip file, named by your student id, and submit required files in it. 

Download this file to start. It contains 2 directories: "Syn" for synthesis and "Sim" for simulation. If you have made some changes in the given interface between the datapath and the CPU controller to support shifting instructions, keep all those changes in this lab.

Synthesis

The goal of this lab is to have you synthesize the complete datapath with Quartus II design tool and then simulate the whole CPU including the synthesized gate-level datapath and your controller (from lab 6). The VHDL description of your design will be transformed into FPGA hardware. The output of the synthesizer is a gate-level design for a specific device selected. This output can be used as an input to the ModelSim simulator to simulate at gate level, with more realistic information (delays, etc). Information to program an actual device is also generated.

First, create a new project in Quartus II using the "new project wizard".

1. When you start the program, a window will pop out, click "Create a new project"
2. In the next screen, enter the project directory, project name, and top-level entity name. The top-level entity name should be "datapath" unless you change it.
3. In the next screen, add all the files. You can use the "..." button besides the "File Name" box to browse. Use the "SYN" directory from the zip file.
4. In the next screen, select the target device. Use the family "Cyclone IV E" and select "Auto device selected by the Fitter". The design tool will find the device where our design can fit.
5. In the next screen, select the tool change like this:

1. Click Finish and you are done.

Now we've have our project set up in Quartus II.

Next, there are some changes you need to make to make the project synthesizable:

1. Change the memory model by adding a clock signal to it. Now memory operation is synchronized with the falling edge of the clock (Why falling edge?). You can use the memory model provided in the "Sim" directory, this change has been applied to it.
2. Add an output port to the datapath to help debugging. The synthesis tool will make the signals disappear. In order to see what happens after synthesis, we have to specifically assign a signal to the port. This would show contents of ALUOut, RegA, RegB ... depending on your needs when you debug.

After you are done editing, start the synthesis process by clicking this button: 

Simulation

The synthesis tool will generate a gate-level VHDL code for the datapath as well as the delay information. We can simulate this gate-level VHDL code, with delay information, and with your controller (from lab 6), in ModelSim.

First, create a new project with the files in the "Sim" directory.

Second, add the DATAPATH.VHO file generated by the synthesis tool to the project. It should be located under "Syn\simulation\modelsim". 

Next, start simulation. In the "Start Simulation" window, click the "SDF" tab, and add the delay information file "XYZ.sdo" like this: (Remember to use INSTANCE names to correctly identify your datapath in the "Apply to Region" box.)

Add signals to the waveform and simulate.

Submission:

• A synthesis report including:
• Device Name
• Total logic elements used
• Total registers used
• Total pins used
• Total memory bits used
• Maximum frequency.

• All your files used for simulation, including the synthesized datapath.
• Screen shots capturing ModelSim Simulation. Capture 3 different types of instructions and show the delays in signal change.