MTRX3760: Mechatronic Systems Design Lab 2

This assignment contributes 10% towards your final mark. It is to be completed individually, not in groups. Total Marks: 100.

This assignment is due before the start of your allocated lab session in two weeks, i.e. before the start of the Week 4 lab session for Weds/Fri labs, and before the start of the Week 5 lab session for Monday labs. Late assignments will be subjected to the University’s late submission policy unless accompanied by a valid special consideration form. Plagiarism will be dealt within accordance with the University of Sydney plagiarism policy. Lab submissions will not be accepted more than a week after the due date.

Assignments will be assessed based on the following components. Incomplete submissions will have severely reduced marks:

● Report: Submit a .pdf report using the class Canvas site. The report can be very simple, and needs only directly address the questions laid out in the assignment.

The cover page for your report should include your SID and tutorial section, but do not include your name to comply with the University’s anonymous marking policy.

Code appendix: The appendix ofyour report must contain a printout (in text format) of all source code written for the assignment. File header comments and proper formatting will be  critical to making this section readable. Unintelligible code attachments will result in loss of marks.

● Code: Submit your code (code only, no binaries) in a .zip file via the canvas site.

Please see Lab 1 for hints on preparing your report, including how to format code for inclusion in the appendix.

Polymorphic Combinatorial Logic Simulator

This lab should be completed with concepts taught in lectures from Weeks 1 and 2.

The logic simulator from Lab 1 was limited to simulating NAND gates. In this example you will apply your knowledge of inheritance and polymorphism to redesign that program. You may start from the code you produced in Lab 1, or redo the program from scratch.

For this assignment all code should follow the coding practices and concepts covered in the Week 1 and 2 lectures, including coding style and use of constructors / destructors.

Make the following changes to the program:

A.  Add the capability to simulate AND, OR, and XOR gates.

B.  Add the capability to instantiate and simulate sub-circuits. A half-adder and the 1-bit comparator shown below are examples of sub-circuits. [2024 Aug 09: circuit corrected]

[https://www.geeksforgeeks.org/magnitude-comparator-in-digital-logic/]

C.   Simulate a two-bit comparator that accepts two 2-bit binary inputs, and generates three outputs, one for each case of equal, less than, or greater than. Your 2-bit comparator should be constructed from 1-bit comparator sub-circuits and a few additional logic gates.

Hints / Simplifications:

●   As in Lab 1 it is acceptable for circuit construction to be hard-coded, but think carefully about where this occurs.

● As in Lab 1 you do not need to split the program (source code) into multiple files.

●   Think back to MTRX1705 to derive the circuit for a 2-bit comparator built from two 1-bit comparators like the one shown above.

●   Work incrementally. Proceed through the steps A-C above one at a time, testing your program at each stage. Do give some thought, in Step A, how you might achieve Step C.

●   Refer back to the checklist provided with Lab 1. Included below is a coding style guideline based on best practices described in lecture.