ECE 303: Real-Time Digital Signal Processing Lab

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Spring 2024

ECE 303: Real-Time Digital Signal Processing Lab

Lab Attendance: Required.

Lab Time:

Lab 001: T/R: 1:00-2:15 PM; Lab 002: M/W/F: 12:05-12:55PM

(1) This is when the lab is guaranteed to be open with either Mark, Mingcong, or Yu there to assist with the assignments. The weekly workload is expected to be about 2.5 hours of work.

(2) The introduction to each lab will be given every Monday/Tuesday.

Organization: Every two students in each group.

Prerequisites: ECE 203 or ECE 330. Experience with MATLAB and C.

Software: MATLAB, Code Composer Studio (CCS), WinDSK8

Hardware: DSP kit : DSP board *1 (OMAP-138LCDK), Power cable *1, USB cable *1, J-TAG emulator *1, 3.5mm audio cable *1

Instructor: Mark Allie, 1538 Engineering Hall, Email: [email protected]Phone: 265-9007

Teaching Assistants:

(1) Mingcong Cao, Email: [email protected]

(2) Yu Huang, Email: [email protected]

Text: Real-Time Digital Signal Processing from MATLAB® to C with the TMS320C6x DSPs, Second Edition ISBN: 978-1439883037. Each group of two students should have at least one copy of the textbook.

Course Website: https://canvas.wisc.edu/courses/425185

The videos linked on the course website are background information on the assignments that may help you complete them.

Goals: This course focuses on implementing Digital Signal Processing ideas and techniques on real-time hardware. At the end of the course, it is expected that you will be able to implement signal-processing tasks on real-time hardware.

Grading: All based on Weekly Assignments and a Final Project, No Midterm/Final exams

Weekly assignments: 10% for each one, totally 80%.    Final Project: 20%

Weekly Assignments: Each week has an associated programming assignment. Each assignment is due by 11:59pm Friday the following weekAssignments will be graded based on the correctness of output and the clarity of your code. Most of the assignments are available at the start of the semester and if you are ambitious, you could have all of the work for the class done early in the semester.

Final Project: TBD


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